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DA255
The DA255 is a fixed-point digital signal processor (DSP) that is capable of achieving high performance and low power through increased parallelism and total focus on reduction in power dissipation. The CPU supports an internal bus structure that is composed of one program bus, three data read buses, two data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to three data reads and two data writes in a single cycle. In parallel, the DMA controller can perform up to two data transfers per cycle independent of the CPU activity.

Features:
  • High-performance, Low-Power, Fixed-Point Digital Signal Processor
  • 9.26-ns Instruction Cycle Time for 108-MHz Clock Rate at 1.2V
  • One/Two Instruction(s) Executed per Cycle
  • Dual Multipliers [Up to 400 Million Multiply-Accumulates per Second (MMACS)]
  • Two Arithmetic/Logic Units (ALUs)
  • Three Internal Data/Operand Read Buses and Two Internal Data/Operand Write Buses
  • 128K x 16-bit On-Chip RAM, composed of:
    • 8 Blocks of 4K 16-bit Dual-Access RAM (DARAM) (64Kb)
    • 24 Blocks of 4K 16-bit Single-Access RAM (SARAM) (192Kb)
  • 32K x 16-bit One-Wait-State On-Chip ROM (64Kb)
  • 8M x 16-bit Maximum Addressable External Memory Space (Synchronous DRAM)
  • 16-bit External Parallel Bus Memory Supporting External Memory Interface (EMIF) with GPIO Capabilities and Glueless Interface.
  • On-Chip Scan-Based Emulation Logic
  • Two 20-bit Timers and a Watchdog Timer
  • Three Multi-channel Buffered Serial Ports
  • Programmable Digital Phase-Locked Loop (DPLL) and Analog Phase-Locked Loop (APLL) Clock Generators
  • Eight General-Purpose I/O (GPIO) Pins and a General-Purpose Output Pin (XF)
  • Supporting Bulk, Interrupt, and Isochronous Transfers
  • Inter-Integrated Circuit (I2C) Interface
  • Real-Time Clock (RTC) With Crystal Input, Separate Clock Domain, Separate Power Supply
  • 4-Channel 10-bit Successive Approximation A/D
  • IEEE Std 1149.1. (JTAG) Boundary Scan Logic
  • 179-Terminal MicroStar BGA (Ball Grid Array)

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